Epson S1D13706 - Page 173

Epson Research and Development
Page 13
Vancouver Design Center
Programming Notes and Examples S1D13706
Issue Date: 01/02/23 X31B-G-003-03
ACh 00 0000 0000 GPIO[6:0] pins are driven low
ADh 00 0000 0000 Set the GPO control bit to low
Bit 7 controls the LCD bias
power for the panel on the
S5U13706B00C.
PWM Clock and CV Pulse Configuration
B0h 00 0000 0000
Selects the following:
• PWMOUT pin is software controlled
• PWM Clock circuitry is disabled
• CVOUT pin is software controlled
• CV Pulse circuitry is disabled
B1h 00 0000 0000 Sets the PWM Clock and CV Pulse divides
For this example the
divides are not required.
B2h 00 0000 0000 Sets the CV Pulse Burst Length
For this example, the burst
length is not required.
B3h 00 0000 0000 Sets the PWMOUT signal to always low
Table 2-1: Example Register Values (Continued)
Register
Value
(Hex)
Value
(Binary)
Description Notes