Epson S1D13706 - Page 417

Epson Research and Development
Page 5
Vancouver Design Center
Interfacing to the Toshiba MIPS TMPR3905/3912 Microprocessors S1D13706
Issue Date: 01/02/23 X31B-G-002-02
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 14
Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
List of Figures
Figure 2-1: Toshiba 3905/12 PC Card Memory/Attribute Cycle . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: Toshiba 3905/12 PC Card IO Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4-1: S1D13706 to TMPR3905/12 Direct Connection. . . . . . . . . . . . . . . . . . . . . .12