Epson Research and Development
Page 5
Vancouver Design Center
Interfacing to 8-bit Processors S1D13706
Issue Date: 01/02/23 X31B-G-015-02
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 12
List of Figures
Figure 4-1: Typical Implementation of 8-bit Processor to S1D13706 Interface . . . . . . . . . . . .11
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