Epson Research and Development
Page 5
Vancouver Design Center
Interfacing to the Intel StrongARM SA-1110 Microprocessor S1D13706
Issue Date: 02/06/26 X31B-G-019-02
List of Tables
Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 4-1: Summary of Power-On/Reset Configuration Options . . . . . . . . . . . . . . . . . . . 14
Table 4-2: CLKI to BCLK Divide Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 4-3: RDFx Parameter Value versus CPU Maximum Frequency . . . . . . . . . . . . . . . . 15
List of Figures
Figure 2-1: SA-1110 Variable-Latency IO Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle . . . . . . . . . . . . . . . . . . . . . . . .10
Figure 4-1: Typical Implementation of SA-1110 to S1D13706 Interface . . . . . . . . . . . . . . .13
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