Epson S1D13706 - Page 662

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Epson Research and Development
Vancouver Design Center
S1D13706 Interfacing to the Intel StrongARM SA-1110 Microprocessor
X31B-G-019-02 Issue Date: 02/06/26
Figure 2-2: illustrates a typical variable-latency IO access write cycle on the SA-1110 bus.
Figure 2-2: SA-1110 Variable-Latency IO Write Cycle
A[25:0]
nCS4
nWE
ADDRESS VALID
DATA VALID
D[31:0]
nOE
nCAS[3:0]
RDY