Fujitsu 8FX User Manual

MB95630H Series
MN702-00009-2v0-E FUJITSU SEMICONDUCTOR LIMITED 509
CHAPTER 24 I
2
C BUS INTERFACE
24.6 Operations and Setting Procedure Example
• Conditions (2) in which no interrupt is generated due to arbitration lost
If the program enables I
2
C bus interface operation (by setting the ICCRn:EN bit to "1") and
triggers a start condition (by setting the IBCR1n:MSS bit to "1") when the I
2
C bus is in use by
another master.
This is because, as shown in Figure 24.6-4, this I
2
C bus interface cannot detect the start
condition (IBSRn:BB = 0) if another master starts communications on the I
2
C bus when the
operation of this I
2
C bus interface has been disabled (ICCRn:EN = 0).
Figure 24.6-4 Timing Diagram with No Interrupt Generated with IBCR0n:ALF = 1
If this situation can occur, use the following procedure to set up the module from the software.
1. Trigger a start condition from the program (by setting the IBCR1n:MSS bit to "1").
2. Check the IBCR0n:ALF and IBSRn:BB bits in the arbitration lost interrupt.
If IBCR0n:ALF = 1 and IBSRn:BB = 0, clear the IBCR0n:ALF bit to "0".
If IBCR0n:ALF = 1 and IBSRn:BB = 1, clear the IBCR0n:ALE bit to "0" and perform
control as normal. (Normal control means writing "0" to the IBCR1n:INT bit in the INT
interrupt to clear IBCR0n:ALF to "0".)
In other cases, perform control as normal (Normal control means writing "0" to the
IBCR1n:INT bit in the INT interrupt to clear IBCR0n:ALF.)
0
0
DataSlave address
Stop
condition
IBCR1n:INT bit interrupt
does not occur in 9th clock cycle.
Start condition
SCLn pin
SDAn pin
ICCRn:EN
IBCR1n:MSS
IBCR0n:ALF
IBSRn:BB
IBCR1n:INT
ACK ACK

Fujitsu 8FX Specifications

General

Brand	Fujitsu
Model	8FX
Category	Computer Hardware
Language	English