CPU 38
Table 3-5 Class: HP_HardwareThread
Property name Property implementation
• 2 (Enabled)
EnabledState
• 3 (Disabled)
For Thread Index 0, it is always enabled.
When Processor is configured, this reflects MultiThread
Status.
RequestedState 12 (Not Applicable)
EnabledDefault 2 (Enabled)
CIM_HardwareThread
• HPQ:HP_ProcessorCore:Cabinet x, Cell y, Socket
z Core m Thread n (for cellular systems)
InstanceID
• HPQ:HP_ProcessorCore: Socket z Core m Thread
n (for non-cellular systems)
HP_HardwareThread
3.3.5HP_ProcessorCacheMemory
HP_ProcessorCacheMemory implements the class HP_CacheMemory which extends CIM_Memory to
model the processor caches.
The following properties are implemented.
Table 3-6 Class: HP_ProcessorcacheMemory
Property name Property implementation
CIM_ManagedElement
Caption One of the following:
• Level x Data Cache, where x is the cache level
number
• Level x Instruction Cache, where x is the cache
level number
• Level x Unified Cache, where x is the cache level
number
• L3 CPU Cache (Integrity servers)
Examples:
• Level 1 Data Cache
• Level 2 Unified Cache
• Level 3 Cache
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