Renesas H8 Series - Page 11

Rev. 7.00 Mar 10, 2005 page xi of xlii
Item Page Revision (See Manual for Details)
1.3.1 Pin
Arrangement
Figure 1.4 Pin
Arrangement (TLP-
85V, H8/38024R
Group, H8/38024S
Group)
12 Title amended
1.3.2 Pin Functions
Table 1.5 Pin
Functions
20, 24 Table amended and note 5 added
Pin No.
Type Symbol
FP-80A
TFP-80C
FP-80B TLP-85V
Pad
No.
*
1
Pad
No.
*
2
Pad
No.
*
3
I/O Name and Functions
X
1
6 8 D3 6 7 6 InputClock
pins
X
2
7 9 D2 7 8 7 Output
These pins connect to a
32.768-kHz or 38.4-kHz
*
5
crystal oscillator.
See section 4, Clock
Pulse Generators, for a
typical connection
diagram.
5. Does not apply to H8/38124 Group.
2.8.1 Memory Map
Figure 2.16(1)
H8/38024,
H8/38024S, and
H8/38124 Memory
Map
61 Figure amended
HD64338024 (mask ROM version)
HD64338024S (mask ROM version)
HD64338124 (mask ROM version)
HD64738024 (PROM version)
Figure 2.16(3)
H8/38022,
H8/38022S, and
H8/38122 Memory
Map
63 Figure replaced
2.9.1 Notes on Data
Access
Figure 2.17 Data
Size and Number of
States for Access to
and from On-Chip
Peripheral Modules
67 Notes amended
3. Only the HD64F38024, HD64F38024R, HD64F38122, and HD64F38124 are equipped with
internal I/O registers from H'F020 to H'F02B and on-chip RAM from H'F780 to H'FB7F.
Attempting to access these areas on products other than the HD64F38024, HD64F38024R,
HD64F38122, and HD64F38124 will result in access to an empty area.
3.3.2 Interrupt
Control Registers
Interrupt Request
Register 1 (IRR1)
Bit 7
85 Table amended
Setting conditions:
When the timer A counter value overflows