Renesas H8 Series Hardware Manual

Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 82 of 652
REJ09B0042-0700
Bit 2—IRQAEC Interrupt Enable (IENEC2)
Bit 2 enables or disables IRQAEC interrupt requests.
Bit 2
IENEC2 Description
0 Disables IRQAEC interrupt requests (initial value)
1 Enables IRQAEC interrupt requests
Bits 1 and 0—IRQ
1
and IRQ
0
Interrupt Enable (IEN1 and IEN0)
Bits 1 and 0 enable or disable IRQ
1
and IRQ
0
interrupt requests.
Bit n
IENn Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 1 or 0)
Interrupt Enable Register 2 (IENR2)
Bit
Initial value
Read/Write
7
IENDT
0
R/W
6
IENAD
0
R/W
5
—
—
W
4
IENTG
0
R/W
3
IENTFH
0
R/W
0
IENEC
0
R/W
2
IENTFL
0
R/W
1
IENTC
0
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Direct Transfer Interrupt Enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT Description
0 Disables direct transfer interrupt requests (initial value)
1 Enables direct transfer interrupt requests

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English