Renesas H8 Series - Page 129

Section 3 Exception Handling
Rev. 7.00 Mar 10, 2005 page 87 of 652
REJ09B0042-0700
Bit 6—A/D Converter Interrupt Request Flag (IRRAD)
Bit 6
IRRAD Description
0
Clearing conditions: (initial value)
When IRRAD = 1, it is cleared by writing 0
1
Setting conditions:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
Bit 5—Reserved
Bit 5 is reserved: it can only be written with 0.
Bit 4—Timer G Interrupt Request Flag (IRRTG)
Bit 4
IRRTG Description
0 Clearing conditions: (initial value)
When IRRTG = 1, it is cleared by writing 0
1 Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Bit 3—Timer FH Interrupt Request Flag (IRRTFH)
Bit 3
IRRTFH Description
0 Clearing conditions: (initial value)
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode