Renesas H8 Series

Section 6 ROM
Rev. 7.00 Mar 10, 2005 page 151 of 652
REJ09B0042-0700
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Input data Output data
Verify
Address
Data
V
PP
VPP
tAS tAH
tDS tDH tDF
tOEtOEStPW
tOPW
*
t
VPS
tVCS
tCES
VCC
VCC
CE
PGM
OE
V
CC
+1
VCC
Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing