Section 9 Timers
Rev. 7.00 Mar 10, 2005 page 267 of 652
REJ09B0042-0700
Bit 3—Toggle Output Level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL Description
0 Low level (initial value)
1 High level
Bits 2 to 0—Clock Select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external
event input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0 Description
000
001
Counting on external event (TMIF) rising/falling edge
*
(initial value)
010
011Use prohibited
100Internal clock: counting on φ/32
101Internal clock: counting on φ/16
110Internal clock: counting on φ/4
111Internal clock: counting on φw/4
Note: * External event edge selection is set by IEG3 in the IRQ edge select register (IEGR). For
details, see IRQ Edge Select Register (IEGR) in section 3.3.2.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register 1
(PMR1) is changed from 0 to 1 or from 1 to 0 while the TMIF pin is low in order to change
the TMIF pin function.
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