Renesas H8 Series Hardware Manual

Appendix A CPU Instruction Set
Rev. 7.00 Mar 10, 2005 page 538 of 652
REJ09B0042-0700
Mnemonic Operation I H N Z V C
MULXU.B Rs, Rd B Rd8 × Rs8 → Rd16 2 14
DIVXU.B Rs, Rd B Rd16÷Rs8 → Rd16 2 (5) (6) 14
(RdH: remainder,
RdL: quotient)
AND.B #xx:8, Rd B Rd8∧#xx:8 → Rd8 2 
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔
↔ ↔ ↔
↔ ↔ ↔
0  2
AND.B Rs, Rd B Rd8∧Rs8 → Rd8 2  0  2
OR.B #xx:8, Rd B Rd8∨#xx:8 → Rd8 2  0  2
OR.B Rs, Rd B Rd8∨Rs8 → Rd8 2  0  2
XOR.B #xx:8, Rd B Rd8⊕#xx:8 → Rd8 2  0  2
XOR.B Rs, Rd B Rd8⊕Rs8 → Rd8 2  0  2
NOT.B Rd B Rd → Rd 2  0  2
SHAL.B Rd B 2  2
SHAR.B Rd B 2  02
SHLL.B Rd B 2  02
SHLR.B Rd B 2  002
ROTXL.B Rd B 2  02
ROTXR.B Rd B 2  02
b
7
b
0
0C
C
b
7
b
0
b
7
b
0
0C
b
7
b
0
0C
C
b
7
b
0
Cb
7
b
0
#xx: 8/16 Rn @Rn @(d:16, Rn) @−Rn/@Rn+ @aa: 8/16 @(d:8, PC) @@aa Implied No. of States
Addressing Mode/
Instruction Length (bytes)
Condition Code
Operand Size

Renesas H8 Series Specifications

General

Brand	Renesas
Model	H8 Series
Category	Computer Hardware
Language	English