Appendix A CPU Instruction Set
Rev. 7.00 Mar 10, 2005 page 539 of 652
REJ09B0042-0700
Mnemonic Operation I H N Z V C
ROTL.B Rd B 2
↔
↔
↔
↔
↔
↔
02
ROTR.B Rd B 2 02
BSET #xx:3, Rd B (#xx:3 of Rd8) ← 12 2
BSET #xx:3, @Rd B (#xx:3 of @Rd16) ← 14 8
BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 14 8
BSET Rn, Rd B (Rn8 of Rd8) ← 12 2
BSET Rn, @Rd B (Rn8 of @Rd16) ← 14 8
BSET Rn, @aa:8 B (Rn8 of @aa:8) ← 14 8
BCLR #xx:3, Rd B (#xx:3 of Rd8) ← 02 2
BCLR #xx:3, @Rd B (#xx:3 of @Rd16) ← 04 8
BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 04 8
BCLR Rn, Rd B (Rn8 of Rd8) ← 02 2
BCLR Rn, @Rd B (Rn8 of @Rd16) ← 04 8
BCLR Rn, @aa:8 B (Rn8 of @aa:8) ← 04 8
BNOT #xx:3, Rd B (#xx:3 of Rd8) ← 2 2
(#xx:3 of Rd8)
BNOT #xx:3, @Rd B (#xx:3 of @Rd16) ← 4 8
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 4 8
(#xx:3 of @aa:8)
BNOT Rn, Rd B (Rn8 of Rd8) ← 2 2
(Rn8 of Rd8)
BNOT Rn, @Rd B (Rn8 of @Rd16) ← 4 8
(Rn8 of @Rd16)
BNOT Rn, @aa:8 B (Rn8 of @aa:8) ← 4 8
(Rn8 of @aa:8)
#xx: 8/16
Rn
@Rn
@(d:16, Rn)
@−Rn/@Rn+
@aa: 8/16
@(d:8, PC)
@@aa
Implied
No. of States
Addressing Mode/
Instruction Length (bytes)
Condition Code
Operand Size
C
b
7
b
0
C
b
7
b
0