Renesas H8 Series - Page 601

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 559 of 652
REJ09B0042-0700
LVDCR—Low-Voltage Detection Control Register H'86 LVDC
Note: This register is implemented on the H8/38124 Group only.
Bit
Initial value
Read/Write
Note: * These bits are not initialized by resets trigged by LVDR. They are initialized by
power-on resets and watchdog timer resets.
7
LVDE
0
*
R/W
6

0
R/W
5
VINTDSEL
0
R/W
0
LVDUE
0
R/W
2
LVDRE
0
*
R/W
1
LVDDE
0
R/W
4
VINTUSEL
0
R/W
Voltage Rise Interrupt Enable
0
Voltage rise interrupt requests disabled (initial value)
1 Voltage rise interrupt requests enabled
Voltage Drop Interrupt Enable
0
Voltage drop interrupt requests disabled (initial value)
1 Voltage drop interrupt requests enabled
LVDR Enable
0
LVDR resets disabled (initial value)
1 LVDR resets enabled
LVDR Detection Level Select
0
Reset detection voltage 2.3 V (typ.) (initial value)
1 Reset detection voltage 3.3 V (typ.)
Power Supply Rise (LVDU) Detection Level External Input Select
0
LVDU detection level generated by on-chip ladder resistor (initial value)
1 LVDU detection level input to extU pin
Power Supply Drop (LVDD) Detection Level External Input Select
0 LVDD detection level generated by on-chip ladder resistor (initial value)
1 LVDD detection level input to extD pin
LVD Enable
0 Low-voltage detection circuit not used (standby status) (initial value)
1 Low-voltage detection circuit use
3
LVDSEL
0
*
R/W