Renesas H8 Series - Page 606

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 564 of 652
REJ09B0042-0700
AEGSR—Input Pin Edge Select Register H'92 AEC
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AIEGS0 ECPWME 
0
R/W
Event Counter PWM Enable/Disable,
IRQAEC Select/Deselect
0
1
AEC PWM halted, IRQAEC selected
AEC PWM operation enabled, IRQAEC deselected
IRQAEC Edge Select
Bit 2
AIEGS0
0
1
0
1
Bit 3
AIEGS1
0
0
1
1
Falling edge on IRQAEC pin is sensed
Rising edge on IRQAEC pin is sensed
Both edges on IRQAEC pin are sensed
Use prohibited
Description
AEC Edge Select L
Bit 4
ALEGS0
0
1
0
1
Bit 5
ALEGS1
0
0
1
1
Falling edge on AEVL pin is sensed
Rising edge on AEVL pin is sensed
Both edges on AEVL pin are sensed
Use prohibited
Description
AEC Edge Select H
Bit 6
AHEGS0
0
1
0
1
Bit 7
AHEGS1
0
0
1
1
Falling edge on AEVH pin is sensed
Rising edge on AEVH pin is sensed
Both edges on AEVH pin are sensed
Use prohibited
Description