Renesas H8 Series - Page 607

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 565 of 652
REJ09B0042-0700
ECCR—Event Counter Control Register H'94 AEC
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W R/W
1
0
0
ACKH1 ACKH0 ACKL1 ACKL0 PWCK2 PWCK1 PWCK0 
0
R/W
Event Counter PWM Clock Select
Bit 2
PWCK1
0
0
1
1
*
*
Bit 3
PWCK2
0
0
0
0
1
1
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
Description
*: Don't care
Bit 1
PWCK0
0
1
0
1
0
1
AEC Clock Select L
Bit 4
ACKL0
0
1
0
1
Bit 5
ACKL1
0
0
1
1
AEVL pin input
φ/2
φ/4
φ/8
Description
AEC Clock Select H
Bit 6
ACKH0
0
1
0
1
Bit 7
ACKH1
0
0
1
1
AEVH pin input
φ/2
φ/4
φ/8
Description