Renesas H8 Series - Page 608

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 566 of 652
REJ09B0042-0700
ECCSR—Event Counter Control/Status Register H'95 AEC
Bit
Initial value
Read/Write
7
OVH
0
R/W
6
OVL
0
R/W
5

0
R/W
0
CRCL
0
R/W
2
CUEL
0
R/W
1
CRCH
0
R/W
4
CH2
0
R/W
Counter Reset Control L
0
1
ECL is reset
ECL reset is cleared
and count-up function
is enabled
Counter Reset Control H
0
ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up Enable L
0
ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up Enable H
0
ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel Select
0
ECH and ECL are used together as a single-
channel 16-bit event counter
1 ECH and ECL are used as two independent
8-bit event counter channels
Counter Overflow L
0
ECL has not overflowed
1 ECL has overflowed
Counter Overflow H
0
ECH has not overflowed
1 ECH has overflowed
3
CUEH
0
R/W