Renesas H8 Series - Page 609

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 567 of 652
REJ09B0042-0700
ECH—Event Counter H H'96 AEC
Bit
Initial value
Read/Write
7
ECH7
0
R
6
ECH6
0
R
5
ECH5
0
R
0
ECH0
0
R
2
ECH2
0
R
1
ECH1
0
R
4
ECH4
0
R
Count value
3
ECH3
0
R
Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (EC).
ECL—Event Counter L H'97 AEC
Bit
Initial value
Read/Write
7
ECL7
0
R
6
ECL6
0
R
5
ECL5
0
R
0
ECL0
0
R
2
ECL2
0
R
1
ECL1
0
R
4
ECL4
0
R
3
ECL3
0
R
Count value
Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (EC).