Renesas H8 Series - Page 648

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 606 of 652
REJ09B0042-0700
IEGR—IRQ Edge Select Register H'F2 System Control
Bit
Initial value
Read/Write
7

1

6

1

4
IEG4
0
R/W
3
IEG3
0
R/W
0
IEG0
0
R/W
2


W
1
IEG1
0
R/W
5

1

IRQ
0
Edge Select
0 Falling edge of IRQ
0
pin input is detected
Rising edge of IRQ
0
pin input is detected
1
IRQ
1
Edge Select
0 Falling edge of IRQ
1
, TMIC pin input is detected
Rising edge of IRQ
1
, TMIC pin input is detected
1
IRQ
3
Edge Select
0 Falling edge of IRQ
3
, TMIF pin input is detected
Rising edge of IRQ
3
, TMIF pin input is detected
1
IRQ
4
Edge Select
0 Falling edge of IRQ
4
, ADTRG pin input is detected
Rising edge of IRQ
4
, ADTRG pin input is detected
1