Renesas H8 Series - Page 653

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 611 of 652
REJ09B0042-0700
IRR2—Interrupt Request Register 2 H'F7 System Control
Bit
Initial value
Read/Write
7
IRRDT
0
R/(W)
*
6
IRRAD
0
R/(W)
*
5


W
3
IRRTFH
0
R/(W)
*
0
IRREC
0
R/(W)
*
2
IRRTFL
0
R/(W)
*
1
IRRTC
0
R/(W)
*
4
IRRTG
0
R/(W)
*
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
A/D Converter Interrupt Request Flag
0 Clearing condition:
When IRRAD = 1, it is cleared by writing 0
1 Setting condition:
When the A/D converter completes conversion and ADSF is reset
Direct Transition Interrupt Request Flag
0 Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1 Setting condition:
When a SLEEP instruction is executed while DTON is set to 1, and a direct transition is made
Timer FH Interrupt Request Flag
0 Clearing condition:
When IRRTFH = 1, it is cleared by writing 0
1 Setting conditions:
When counter FH and output compare register FH match in 8-bit timer mode,
or when 16-bit counters FL and FH and output compare registers FL and
FH match in 16-bit timer mode
Timer FL Interrupt Request Flag
0 Clearing condition:
When IRRTFL = 1, it is cleared by writing 0
1 Setting condition:
When counter FL and output compare register FL match in 8-bit
timer mode
Timer G Interrupt Request Flag
0 Clearing condition:
When IRRTG = 1, it is cleared by writing 0
1 Setting conditions:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
Timer C Interrupt Request Flag
0 Clearing condition:
When IRRTC = 1, it is cleared by writing 0
1 Setting condition:
When the timer C counter value overflows (from H'FF to
H'00) or underflows (from H'00 to H'FF)
Asynchronous Event Counter Interrupt Request Flag
0 Clearing condition:
When IRREC = 1, it is cleared by writing 0
1 Setting condition:
When the asynchronous event counter value
overflows