Renesas H8 Series - Page 655

Appendix B Internal I/O Registers
Rev. 7.00 Mar 10, 2005 page 613 of 652
REJ09B0042-0700
IWPR—Wakeup Interrupt Request Register H'F9 System Control
Bit
Initial value
Read/Write
7
IWPF7
0
R/(W)
*
6
IWPF6
0
R/(W)
*
5
IWPF5
0
R/(W)
*
3
IWPF3
0
R/(W)
*
0
IWPF0
0
R/(W)
*
2
IWPF2
0
R/(W)
*
1
IWPF1
0
R/(W)
*
4
IWPF4
0
R/(W)
*
0
Clearing condition:
When IWPFn = 1, it is cleared by writing 0
(n = 7 to 0)
Note: * All bits can only be written with 0, for flag clearing.
Wakeup Interrupt Request Register
1 Setting condition:
When pin WKPn is designated for wakeup input and a
falling edge is input at that pin