register returns a decimal value of the binary-weighted sum of all bits set in the
register.
Enable Register
An enable register is both readable and writable, used to define which status
information will be reported to the next level. Querying an enable register will not
clear bits in it. Sending the clear status command
*CLS
will not clear bits in the enable
register (but the command
*CLS
does clear the bits in the event registers). To enable
bits in an enable register, you must write a decimal value which corresponds to the
binary-weighted sum of the bits you wish to enable in the register.
Multiple Logical Output
It is only applicable to multi-channel models. Take DP2031 as an example. The three
logical outputs of the power supply include a channel questionable status register
and three independent channel questionable status SUMMARY registers
(corresponding to the logical outputs of the three channels respectively). The channel
questionable status SUMMARY registers report the status of each channel to the
channel questionable status register, which in turn reports the channel status to bit13
(ISUM bit) of the Questionable status register.
SCPI Status Register
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