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Tightly-Coupled Memory Interface

In cycle T5, the access to A completes. A sequential request is made to A+1. There is

no DMA activity.

In cycle T6, the access to A+1 completes. A sequential request is made to A+2. There

is no DMA activity

In cycle T7, the access to A+2 completes. No request is made and DRCS is deasserted.

A DMA access to address C starts and DRWAIT is asserted using DMAWAIT.

In cycle T8, DRWAIT remains HIGH because of DMA access. No request is made, and

DRCS remains LOW.

In cycle T9, the DMA access to C completes. A nonsequential request is made to

address D.

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ARM ARM926EJ-S Specifications

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