Bus Interface Unit
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 6-11
For all other types of access (cache linefills, writeback evictions, buffered writes), an
Error response is ignored.
If the ARM926EJ-S processor is to be used in a system which has to be tolerant to soft
errors in external memory, then both soft error detection and correction must be done in
hardware at the time the AHB transfer is made. The DHREADY and IHREADY
signals can be used to extend the transfer until corrected data is available.
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