Noncachable Instruction Fetches
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. 7-3
This IMB implementation only applies to the ARM926EJ-S processor running code
from a noncachable region of memory. If code is run from a cachable region of memory,
or a different device is used then a different IMB implementation is required. IMBs are
described in Chapter 9 Instruction Memory Barrier.
7.1.3 AHB behavior
If instruction prefetching is disabled, all instruction fetches appear on the AHB interface
as single, nonsequential fetches.
If prefetching is enabled then instruction fetches either appear as bursts of four
instructions, or as single, nonsequential fetches. No speculative instruction fetching is
done across a 1KB boundary.
All instruction fetches, including those made in Thumb state, are word transfers (32
bits). In Thumb state a single-word instruction fetch reads two Thumb instructions, and
a four-word burst reads eight instructions.
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