Signal Descriptions
A-6 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
CHSEX[1:0]
Coprocessor
handshake execute
Input The handshake signals from the Execute stage of the
coprocessors pipeline follower. Indicates ABSENT
(10), WAIT (00), GO (01), or LAST (11). If no
external coprocessors are attached these must be tied
to b10 (ABSENT response).
nCPINSTRVALID
Coprocessor valid
instruction
Output Valid instruction indicator for CPINSTR (replaces
CPTBIT).
nCPMREQ
Not coprocessor
instruction request
Output If this signal is LOW on the rising edge of CLK and
CPCLKEN is HIGH, the instruction on CPINSTR
must enter the coprocessor pipeline.
nCPTRANS
Not coprocessor
memory translate
Output When LOW the coprocessor interface is in a
nonprivileged state. When HIGH the coprocessor
interface is in a privileged state.
Table A-2 Coprocessor interface signals (continued)
Name Direction Description
To Next Page
Loading...
