Signal Descriptions
A-16 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
IRDMAADR[17:0] Input DMA access cycle.
If asserted, IRADDR is directly sourced from
IRDMAADDR, and IRCS is the result of logically
ORing IRDMACS with the chip select value for the
current TCM access.
IRDMAEN Input Enables direct memory access to the ITCM memory
using the IRDMAADDR and IRDMACS inputs.
IRDMACS Input Direct memory access chip-select for ITCM.
IRIDLE Output Instruction TCM interface idle:
0 = TCM access
1 = no access will take place in the current cycle or
TCM disabled.
Not valid for DMA accesses.
IRnRW Output Instruction TCM read not write:
0 = read
1 = write.
Indicates if the access is a read or write. Valid during
request cycles.
IRRD[31:0] Input Instruction TCM read data.
Valid during non-waited data cycles.
IRSEQ Output Request sequential.
Valid during request cycles, asserted during wait
cycles.
Indicates that the address in the current cycle is
sequential to the address used during the previous
request cycle.
IRSEQ is not valid following ITCM DMA accesses.
IRSIZE[3:0] Input Instruction TCM size.
Static configuration input that specifies the physical
size of TCM memories attached.
0000 = absent
0011 = 4KB
0100 = 8KB
…
1010 = 512KB
1011 = 1MB
Values 0001, 0010, and 1100 to 1111 are reserved.
Table A-7 TCM interface signals (continued)
Signal Direction Function
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