Signal Descriptions
ARM DDI0198D Copyright © 2001-2003 ARM Limited. All rights reserved. A-17
IRWAIT Input Instruction TCM wait state input.
If HIGH, the ITCM cannot service the request in that
cycle.
Valid in request cycle and subsequent wait cycles.
Ignored if not a request or wait cycle.
IRWBL[3:0] Output Instruction TCM write data byte lane indicator.
Valid during request cycles.
For reads, set to b0000
For writes indicates which byte(s) are to be written,
depending on the address and the size of the access
(word, halfword, or byte).
Bits of IRWBL are set only when a write is taking
place, so when IRnRW is unset all the bits of
IRWBL are also unset.
IRWD[31:0] Output Instruction TCM write data.
Valid during request cycles when IRnRW is 0.
Valid during waited write cycles.
Table A-7 TCM interface signals (continued)
Signal Direction Function
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