Programmer’s Model
2-14 Copyright © 2001-2003 ARM Limited. All rights reserved. ARM DDI0198D
Effects of Control Register on caches
The bits of the Control Register that directly affect the ICache and DCache behavior are:
• the M bit
• the C bit
• the I bit
[13] V bit Location of exception vectors:
0 = Normal exception vectors selected, address range =
0x0000 0000
to
0x0000 001C
1 = High exception vectors selected, address range =
0xFFFF 0000
to
0xFFFF 001C
.
Set to the value of VINITHI on reset.
[12] I bit ICache enable/disable:
0 = ICache disabled
1 = ICache enabled.
[11:10] - SBZ.
[9] R bit ROM protection.
This bit modifies the ROM protection system. See Domain access
control on page 3-24.
[8] S bit System protection.
This bit modifies the MMU protection system. See Domain access
control on page 3-24.
[7] B bit Endianness: 0 = Little-endian operation 1 = Big-endian operation. Set to
the value of BIGENDINIT on reset.
[6:3] - Reserved. SBO.
[2] C bit DCache enable/disable:
0 = Cache disabled
1 = Cache enabled.
[1] A bit Alignment fault enable/disable:
0 = Data address alignment fault checking disabled
1 = Data address alignment fault checking enabled.
[0] M bit MMU enable/disable:
0 = disabled
1 = enabled.
Table 2-11 Control bit functions register c1 (continued)
Bit Name Function
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