SYSTEM BOARD
TO/FROM
MEMORY
EXPANSION
DAUGHTER
BOARD
MEMORY
SUBSYSTEM
DIAGNOSTIC _
TO/FROM
F
•
SYSTEM
SUBSYSTEM
CONSOLE
S-BUS
SYSTEM
PROCESSING
UNIT
INPUT/OUTPUT
SUBSYSTEM
ECLIPSE I/O BUS I I
I I BMC BUS
- TO/FROM -
I/O DEVICE CONTROLLERS
FS-12747
Figure 3-2. ECLIPSE MV/7800 Subsystem Organization
At the heart of the system processing unit, memory, and input/output subsystems are very large-scale integrated
circuit (VLSI) chips, which are part of the micro MV chip set. The micro MV chip set, a VLSI implementation of
the ECLIPSE MV/architecture, includes: a central processing unit (CPU) chip; microsequencer (uSEQ) chip;
floating-point unit (FPU) chip; input/output (PIO/DCH) controller chip; a burst multiplexor channel (BMC)
controller chip; and a memory control unit (MCU) chip. These chips collectively deliver the processing
performance to the MV/7800 computer. The CPU, uSEQ and FPU chips form the nucleus of the system
processing unit (SPU). The MCU chip is the center of the memory subsystem. The PIO/DCH and BMC
controller chips form the center of the input/output (I/O) subsystem. The diagnostic subsystem is run by an Intel
8031 microprocessor which is not part of the micro MV chip set.
Figure 3-3 shows the micro MV chip set and other major functional elements of the ECLIPSE MV/7800 system
within their subsystem groupings.
043-003621
3-2
DGC
CONFIDENTIAL - INTERNAL USE ONLY
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