DCH Output Data Cache
If an I/O device controller specifies a DCH output operation, the DCH control logic locates the output data and
places it on the ECLIPSE I/O bus. In many cases, the data for the output operation is supplied by the DCH
output data cache. This cache is closely associated with the DCH map cache. Appended to each of the six entries
of the DCH map cache is an output data cache entry that can buffer one or two words of data from the memory
page addressed by the DCH map cache entry. The output data cache entry is examined whenthe corresponding
DCH map cache entry contains the correct address translation for a DCH output operation.
Data is loaded into the output data cache by a memory read during a DCH output operation or by an explicit data
prefetch. The DCH control logic prefetches output data to enhance DCH output performance. When an output
operation involves an odd-addressed word of data, whether accessed from the output cache or system memory,
the DCH control logic increments the address and uses it to fetch the next double-word from system memory.
This double-word is stored in the output data cache to await its anticipated use by subsequent DCH output
operations.
The DCH outputs data cache and output data cache prefetch are enabled or disabled by writing to the PIO/DCH
control register. The DCH map cache must be enabled to use the output data cache.
3.2.12 ECLIPSE Input/Output Bus
The ECLIPSE input/output (I/O) bus connects the PIO/DCH chip to all peripheral controller interfaces and
handles both PIO and data channel transfers within the ECLIPSE MV/7800 computer system.
Data and addresses are transferred on this bus along 16 parallel, bidirectional, data lines. Data and address
transfers are synchronous; so no handshaking occurs between the peripheral controller interface and the
PIO/DCH controller. Dedicated control lines carry 32 signals that specify the unique function to be performed.
Each control signal generated by the PIO/DCH controller provides all timing necessary to perform that function.
The PIO and DCH control logics must share access to the data and device select lines, as well as control of the
request enable signal. The current operation in progress is always allowed to finish. However, as long as a DCH
request has not been acknowledged, a PIO operation request will be given priority.
The data channel and program interrupt facility each have a dedicated request and priority line. The two request
lines run in parallel to all peripheral controllers, so that a controller requiring either data channel or program
interrupt service need only assert the appropriate line and wait for the response. The serial priority lines are
independent and are chained from controller to controller, so that the priority for service is granted to the
controller physically closest on the chain to the PIO/DCH controller.
With the exception of two priority lines, all signal lines run in parallel between the PIO/DCH controller and the
peripheral controllers connected to the bus.
3.2.13 Burst Multiplexor Channel Controller
The Burst Multiplexor Channel (BMC) controller transfers variable length bursts of data between the BMC bus
and the ECLIPSE MV/7800 S-bus as a path to system memory. Physically, the BMC controller has been created
from a CMOS gate-array.
043-003621
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DGC CONFIDENTIAL - INTERNAL USE ONLY
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