Control Unit
The control unit in the MCU is a simple state machine. The PROMs, external to the MCU, store control
instruction sequences used by this state machine to execute memory operations. In general, the state machine
begins each memory operation in a fixed state selected by its arbitration and encoding logic. It then sequences
directly through the next several states. At the start of the next T-period, the control unit sequencer may extend
the operation (error correction, for example), or it may allow a new operation to start:
Memory Operations
Most memory operations are initiated by the SPU, PIO/DCH controller, or BMC controller driving an address and
its associated operation code (opcode) onto the S-bus during the first half of a bus cycle. The MCU enables the
transfer of this information from the S-bus to the M-bus and asserts the address latch enable signal that clocks the
address into the address latch and transceiver. The address is then transferred to the MCU and RAM arrays as
well as to another register in the transceiver where it is saved in case of an ERCC error. The opcode is sent to the
MCU where it is decoded to specify a sequence of instructions stored in the MCU's external PROMs.
To execute a memory operation, the MCU asserts the memory start signal that is synchronized to the system
master clock. The row address select (RAS) and column address select (CAS) logic, which are external to the
MCU, are controlled by a delay line that is also synchronized to the system master clock. This enables the RAS
and CAS signals to be asserted to the RAM arrays at the appropriate time.
During the second half of the bus cycle, or subsequent cycles for extended operations, data is driven onto the
system bus by either the memory (read operation) or the SPU, PIO/DCH controller, or BMC controller (write
operation). The MCU steps through the specified sequence of instructions to execute the memory operation.
If the operation is a memory read, the MCU enables the contents of the data-out buffer onto the M-bus. The
MCU forces the S-M transceiver to drive the data from the M-bus to the S-bus.
If the operation is a double-word memory write, the MCU waits until the data phase (the second half of the
M-bus cycle), for the data to appear on the S-bus, and then drives the data onto the M-bus. It then loads the
data into the memory data-in latch and completes the operation.
Partial write operations are more complicated to control. The MCU performs a read operation but does not
source the read data onto the M-bus. Instead, the write data on the S-bus is driven onto the M-bus and latched
into the MCU data register. The MCU then sources the read data onto the M-bus and merges that data into its
internal register, overwriting the write data bytes that must not change during the write. The MCU data register is
driven back out onto the M-bus and a write to memory is performed.
When the operation is complete, the MCU signals to the SPU, PIO/DCH controller, and BMC controller that is
ready to handle another memory operation request. If an error occurs, the complete memory address and the
syndrome are transferred to the error address latch to be saved until the CPU requests the error information.
3.2.11 Input/Output Subsystem
The ECLIPSE MV/7800 input/output (I/O) subsystem handles all communications with the system peripherals.
These communications take place over the standard ECLIPSE I/O bus or the burst multiplexor channel (BMC)
bus.
Information transfers over the ECLIPSE I/O bus are either programmed I/O (PIO) or data channel operations.
Both types of transfers are handled by the PIO/DCH controller. A PIO operation is CPU-initiated and executed
by the PIO/DCH controller. This type of operation transfers a single byte or work between an accumulator and a
peripheral device. Data channel operations transfer a block of words between a peripheral device and system
memory via the ECLIPSE I/O bus. Data channel operations are set up using PIO and executed by the PIO/DCH
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