Two buses interconnect the functional elements of the execution unit: the A bus and the B bus. The A bus passes
operands from the register file to the sign, mantissa, and exponent ALUs. The 8 bus conveys data to and from all
the sections of the FPU.
3.2.9.3 System Bus (S-bus) Interface - The S-bus interface is the data link between the FPU and the rest of
the ECLIPSE MV/7800 system. It consists of the bus interface register, the floating-point status register, and the
logic that control them. The bus interface register is a 64-bit, dual-ported register between the FPU internal B
bus and the ECLIPSE MV/7800 S-bus. The bus interface register appears to the FPU internal logic as a 64-bit
source and destination on the B bus. To the S-bus, the bus interface register appears as two 32-bit memory
locations in FPU local space. This register, accessible to both FPU and CPU, provides a communications path
between both these processing elements of the SPU. The floating-point status register (FPSR) is a 64-bit register
that contains information on the state of the elements in the FPU execution unit, and a floating-point program
counter. The FPSR is accessible to the S-bus as two locations in FPU local space. The control logic determines
when data is written into the bus interface register and FPSR, and when data in these registers is driven onto the
buses.
3.2.10 Memory Subsystem
The memory subsystem provides the physical address space for the ECLIPSE MV/7800 system memory. This
subsystem consists of dynamic RAM memory arrays, the memory bus (M-bus), various latches and transceivers
which interface to the system bus, and a memory control unit (MCU) gate array, whose functions include timing,
error checking and correction (ERCC), refresh, and memory operation executions.
Memory sized for the ECLIPSE MV/7800 system are two, or four on the system board, and two, four or 10
megabytes on the memory expansion daughter board, for a total of up to 14 megabytes. The 7-inch x 15-inch
daughter board mounts on top of the system (mother) board and contains surface-mounted dynamic RAMs
(DRAMs), various latches, drivers, and control logic.
3.2.10.1 Memory Bus - The memory bus (M-bus) is a 32-bit bidirectional bus which connects to the system bus
through a registered transceiver and is used primarily for passing addresses and data between system memory and
the SPU and I/O subsystems. Its timing, protocol, and maximum transfer rate are similar to that of the system
bus.
3.2.10.2 Dynamic RAM Arrays - The onboard system memory consists of a 2- or 4- Mbytes dynamic RAM
memory array comprised of 256 X 1 bit RAM elements that are organized into four noninterleaved rows of 256k
X 39 bit words each. The access time for these RAMs is 100 nanoseconds. The expansion memory daughter
board contains up to 10 Mbytes of a similar dynamic RAM memory.
3.2.10.3 External Address Registers and Transceivers - An MCU controlled registered transceiver (S-M
transceiver) connects the S-bus to the M-bus, and saves addresses in both directions. While an address is on the
M-bus, the MCU clocks the address in to a register inside the S-M transceiver. The address is saved there so it
can be transferred into the MCU as well as another register in the S-M transceiver, where it is stored in case of an
ERCC error. An address latch, and data-out buffer connect the M-bus to the dynamic RAMs and provide
temporary information buffering.
3.2.10.4 Memory control Unit - The Memory Control Unit (MCU) is a gate array designed to control the
dynamic RAM array and its interface to the system bus. The major functional elements within the MCU gate array
are the data unit, address unit, and control unit. The data unit performs the error checking and correction
(ERCC) functions and buffers data words. The address unit generates addresses for memory refresh operations.
The control unit contains the state machine and various decoders and circuits used to control the memory
DGC CONFIDENTIAL - INTERNAL USE ONLY
3-17
043-003621
To Next Page
Loading...