the system, several flags, and a six-entry stack for microsubroutines. The sequencer also provides the ability to
save its state in the event of a page fault.
3.2.8.7 Control Store - The control store is external to the uSEQ chip. It consists of 16K X 40 bits of MOS
RAM, organized into 40-bit microwords. Each microword contains a 24-bit vertical microinstruction for the
execution chips and a 16-bit sequencing instruction.
The microcode for the ECLIPSE MV/7800 kernel instruction set is stored in the diagnostic remote processor
(DRP) ROM address space. Upon initial power-up, the DRP down loads the kernel microcode directly into the
control store. Later in the power-up sequence, the rest of the instruction set microcode is loaded into the control
store from the system load device.
3.2.9 Floating-Point Unit
The Floating-Point Unit (FPU) performs all floating-point operations. The FPU contains three major functional
units: the control unit, the execution unit, and the S-bus interface. The control unit receives vertical
microinstructions from the SPU control store and uses them to generate horizontal control signals for its execution
unit and S-bus interface. The execution unit performs the data manipulation. The S-bus interface provides
communication between the execution unit and the
-
other elements in the ECLIPSE MV/7800 system. Figure 3-7
shows the major functional elements of the FPU:
•
Control unit
•
Execution unit
•
S-bus interface
3.2.9.1 Control Unit - The FPU control unit receives vertical microinstructions from the SPU control store and
uses them to initiate a sequence of horizontal microinstructions that control the execution unit and S-bus
interface. The control unit consists of a small pipeline for receiving vertical microinstructions, a horizontal
programmable logic array (HPLA) for storing horizontal microinstructions, and a sequencer for the HPLA. The
vertical pipeline consists of two registers arranged in parallel. One register contains the currently executing vertical
microinstruction while the other register contains the currently executing vertical microinstruction while the other
register contains the next vertical microinstruction from the uSEQ instruction stream. The HPLA sequencer takes
a starting address from the currently executing vertical microinstruction and uses it to access horizontal
microinstructions in the HPLA. These horizontal microinstructions contain the control signals that direct the
operation of the execution unit.
3.2.9.2 Execution Unit - The execution unit performs the actual data manipulation within the FPU. The data
representing each floating-point number is organized into a sign, an exponent, and a fractional part called the
mantissa. The execution unit manipulates these sections of data individually; it consists of a sign ALU, an
exponent ALU, and a mantissa ALU. The sign ALU is a two-input unit capable of setting its output to either
input or the result of a variety of logical operations performed on the inputs. The exponent ALU is a 8-bit wide
adder with associated logic to subtract, increment, and decrement. The mantissa ALU is a 66-bit wide arithmetic
unit that provides the combined functions of a carry-propagate adder and a carry-save adder.
The execution unit also includes a decimal constant ROM, a dual-port register file, a normalization scanner, a
nibble shifter, and a division PLA with its associated logic. The dual-port register file consists of four 64-bit
floating-point accumulators and four microcode-accessible, general-purpose registers for temporary register
space. The normalization scanner evaluates the output of the mantissa ALU and determines the number of
necessary nibble mantissa. (A nibble is four bits or one-half byte.) The nibble shifter, which works in conjunction
with the normalization scanner, aligns and normalizes the mantissa before and after it is operated upon by the
mantissa ALU. The division logic and PLA implement a fixed-point division algorithm that uses
two-bit-per-cycle quotient estimation.
DGC CONFIDENTIAL - INTERNAL USE ONLY
3-15
043-003621
To Next Page
Loading...