3.2.8.1 Instruction Register (IR) Pipeline - The uSEQ IR pipeline is identical to the IR pipeline in the CPU
instruction prefetcher. It contains five 16-bit storage elements that collectively function as a first-in-first-out
queue used to store prefetched instructions. The uSEQ bus interface logic transfers prefetched double words of
instructions from the S-bus to the IR pipeline. The IR pipeline control logic keeps track of how many words are
currently contained in the pipeline and loads the incoming data directly into the appropriate pipeline location.
The 16-bit output of the IR pipeline contains decode information and provides the input for the uSEQ decode
logic. Once an instruction has been decoded, it is deleted from the pipeline, allowing additional instructions to be
pre fetche d .
3.2.8.2 Microsequencer - CPU Synchronization - Since the uSEQ IR pipeline is identical to the CPU IR
pipeline, both pipelines must be synchronized to ensure proper coordination of the uSEQ and the CPU.
Synchronization is accomplished using two time-multiplexed IR pipeline control signals transmitted from the CPU
to the uSEQ. When the CPU initiates an instruction fetch from memory, it notifies the uSEQ using the IR pipeline
control signals. this synchronization enables the uSEQ to take the instructions from the S-bus at the appropriate
time. Also, when displacement information or immediate operands are included in the instruction stream, the
CPU takes them from the CPU IR pipeline and signals to the uSEQ that the corresponding data in the uSEQ IR
pipeline should be discarded. The CPU also indicates to the uSEQ when the entire contents of the IR pipeline
should be discarded (flushed).
3.2.8.3 Decode Logic - When the execution of the microroutine for an assembly-language instruction finishes,
the sequencing logic initiates another instruction decode. The instruction decode passes control back to the
decode logic to determine the next microroutine to be executed. The uSEQ is initialized based on the next
instruction in the IR pipeline, and the appropriate microroutine begins executing. The decode logic consists of the
starting programmable logic array (SPLA) and the flag programmable logic array (FPLA).
3.2.8.4 Starting Programmable Logic Array - The starting programmable logic array (SPLA) decodes the
16-bit output of the IR pipeline to access one of its entries, which consists of a 24-bit vertical microinstruction and
a 16-bit sequencing instruction decode or the address of a control store entry which contains the next
microinstruction to be executed.
Frequently used assembly-language instructions may decode to unique SPLA entries for optimum performance.
Most instructions, however, share an SPLA entry with other assembly-language instructions in order to limit the
total size of the SPLA. The instructions which share the same SPLA entry are distinguished by differing FPLA
entries.
3.2.8.5 Flag Programmable Logic Array - The flag programmable logic array (FPLA) contains information
that is used in conjunction with the SPLA to identify which microroutine is needed to execute an
assembly-language instruction. The uSEQ contains four flags that are initialized at decode time and can be tested
or set by microcode. The initial values of the flags from the output of the IR pipeline are decoded and reset by the
FPLA. The output of the FPLA and the SPLA determine which microinstruction(s) the execution chips receive.
3.2.8.6 Sequencing Logic - The sequencing logic uses the current state of the uSEQ and the sequencing
instruction provided by the control store to select the sequence of microinstructions (microroutine) for executing
an assembly-language instruction.
Once the SPLA decodes an assembly-language instruction and the SPLA sequencing instruction specifies the use
of an address rather than another instruction decode as the path to the next microinstruction, the uSEQ begins
sequencing through the appropriate microinstructions in the control store, and continues to do so until another
decode is needed. Subsequent sequencing instructions come from the control store itself and determine how the
address of the next microinstruction is generated, based on the state of the elements in the sequencing logic.
These elements include a microprogram counter, decision logic that determines an address based on the state of
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