SYSTEM BUS (32 BITS)
I CENTRAL
MICRO- I
PROCESSING
SEQUENCER
UNIT
FLOATING-
POINT
UNIT
NEXT ADDRESS
I I MICROADDRESS
BUFFER
I I
BUFFER
<
-
MICRO-
CONTROL STORE
ADDRESS
16K X 40 RAM
REPEATER
I NEXT ADDRESS I
I
LATCH
I MICROADDRESS I
LATCH
FS-12749
Figure 3-4. System Processing Unit Block Diagram
3.2.2 Central Processing Unit
The Central Processing Unit (CPU) in the SPU is a 32-bit microprogranuned processor. The CPU executes the
standard ECLIPSE MV/Family 32-bit instruction set, translates logical addresses, and accesses memory. The
CPU also interfaces with other SPU elements and system elements via the S-bus, znicrocontrol bus, and various
control signals. Physically, the CPU is a single VLSI chip. Figure 3-5 shows the major functional elements of the
CPU:
•
Fixed-point arithmetic unit
•
Address translation unit
•
Instruction prefetcher
•
Control unit
DGC CONFIDENTIAL - INTERNAL USE ONLY
3-9
043-003621
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