3.1 FUNCTIONAL OVERVIEW
3.1.1 System Processing Unit
The System Processing Unit (SPU) delivers the processing power for the MV/7800 computer. The SPU executes
the standard ECLIPSE MV/Family 32-bit instruction set, translates logical addresses, and interfaces with the
memory, I/O, and diagnostic subsystem. Physically, the SPU resides on the system PCB and consists of the uSEQ,
CPU, and FPU chips together with the control store and support logic. These components communicate with each
other over the system bus (S-bus) and the internal SPU 16-bit microaddress bus and the 24-bit microcontrol bus.
3.1.2 Memory Subsystem
The memory subsystem provides the physical memory address space for the MV/7800 computer. The subsystem
consists of a dynamic RAM memory array, address and data latches, transceivers that interface to the S-bus, and
a memory control unit (MCU) gate array. The MCU gate array's functions include timing, error checking and
correction (ERCC), refresh, and memory operation control. The memory subsystem components communicate
with each other over the 32-bit memory bus, which is connected to the S-bus through a set of register
transceivers.
The memory system provides up to four megabytes of dynamic RAM. Additional memory expansion is achieved
by adding a 7-inch by 15-inch daughter-board on top of the system PCB. This expansion board provides up to
10 Mbytes of dynamic RAM and the necessary address and data latches. Thus, with the expansion memory
daughter-board, the system can provide up to 14 Mbytes of physical memory.
3.1.3 Input/Output Subsystem
The MV/7800 input/output (I/O) subsystem handles all communications with the system peripherals. These
communications take place over the standard ECLIPSE I/O bus or the Burst Multiplexor Channel (BMC) bus.
ECLIPSE I/O bus transactions are either programmed I/O (PIO) or data channel operations. Both types of
transactions are handled by the programmed I/O/data channel (PIO/DCH) controller chip. Programmed I/O
operations are CPU-initiated and executed by the PIO/DCH controller. These operations involve transfers of 8 or
16 bits of data or control information. Data channel operations involve the rapid transfer of blocks of data
between a device and system memory via the ECLIPSE I/O bus and S-bus. Special DCH and mapping logic
accelerates the execution of these operations.
The BMC bus transactions allow the peripheral controllers to access the system memory directly at higher speeds
than the data channel. The BMC gate array receives command information from the CPU chip and performs
these BMC transactions.
3.1.4 Diagnostic Subsystem
The diagnostic subsystem supports system power-up, initialization, and remote diagnosis of both hardware and
software problems. The subsystem contains the diagnostic remote processor (DRP) that executes the system
control program (SCP) and contains remote modem interface logic, RAM and ROM used to store the microcode
for Kernel instruction set and power-up, and the time-of-day (TOD) clock/calendar. These components
communicate with each other over an 8-bit remote bus that is connected to the S-bus through a set of registered
transceivers.
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