3.1.9 Data Phase and Transfer Control
The second half of every bus cycle is the data phase during which data is transferred over the bus. Data is
organized into 32-bit (double-word) format, however, the bus also accommodates transfers to individual bytes (8
bits) and words (16 bits). The size and format of the data depends on the type of operation in progress.
Most of the control information needed for the successful transfer of data across the S.-bus is derived from the
basic system timing and from the contents of the busatacidress time. A single, dedicated control line, the
_
READY signal, is defined for controlling the transfer of data.
The READY signal is used to indicate the successful completion of the required data transfer. A bus user that
cannot complete a transfer in the time allotted uses the READY line to extend the transfer into one or more
succeeding bus cycles.
Ready is a three-state, bidirectional signal which is in the high-impedance state during the portion of the bus cycle
(T period) that is normally used for address transfer and is actively driven by exactly one bus user at any other
time. During idle bus cycles, READY is driven by the requestor in control of the bus. During simple bus transfers,
READY is driven by the server in the current transaction.
If READY is unasserted at the end of any T period, the requestor that had planned to drive an address onto the
bus in the next T period is prohibited from doing so. If a simple read or write transfer continues into the next T
period because READY is unasserted, the data transfer is repeated in each succeeding T period until READY is
unasserted. In such cases, the bus remains in a high-impedance state during the address transfer portion of the T
period. READY is a bidirectional signal.
3.1.10 Priority Arbitration
A priority chain and well-defined rules for bus usage guarantee exactly one bus master driving an address onto the
bus at the appropriate time.
The READY and bus lock (LCK) signals and the priority arbitration logic determine which requestor uses the bus
in the next T period. If unasserted, the READY signal causes the current transaction to be continued into the
next T period. If READY is asserted but the bus is locked, only the requestor currently using the bus can and
must use the bus in the next T period. When READY is asserted and the bus is not locked, the bus is available.
Access is determined by the priority arbitration logic. This logic consists of a priority chain for the next-cycle
access that gives priority, from the highest to the lowest, in the following order: the MCU, the PIO/DCH
controller, the BMC controller, and the CPU.
3.2 SYSTEM OPERATION
The System Processing Unit (SPU) executes the standard ECLIPSE MV/Family 32-bit instruction set, translates
logical addresses, and interfaces with the memory, I/O, and diagnostic subsystems. Physically, the SPU resides on
the system PCB and consists of the znicrosequencer (uSEQ), central processing unit (CPU) and floating-point unit
(FPU) chips together with the control store. The SPU communicates with the other ECLIPSE MV/7800
subsystems over the 32-bit bidirectional system bus (S-bus). The elements within the SPU communicate with
each other over the S-bus, the 24-bit microcontrol bus, and the 16-bit rnicroaddress bus.
3.2.1 Operational Overview
The SPU performs the fetching, decoding, and execution of assembly-language instructions within the MV17800
computer. The SPU performs these tasks at a speed accelerated by its pipeline architecture and two level
microcode control.
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