3.2.3 Fixed-Point Arithmetic Logic Unit
The fixed-point arithmetic logic unit performs the data manipulations required to execute most arithmetic and
logic instructions dealing with fixed-point data. The unit contains an arithmetic logic unit (ALU) with its
associated logic, system registers, general-purpose registers, and internal buses.
The ALU performs the actual data manipulations by executing combinations of 26 logic operations. A dual-port
register file, consisting of four 32-bit fixed-point accumulators and eight 32-bit general-purpose registers, supplies
the ALU with register space. These registers are connected to the ALU by two 32-bit wide buses: the A bus and
the
B
bus. A shift register and constant ROM are also included in the ALU.
There are also a number of single-port, special-purpose registers within the fixed-point arithmetic logic unit. The
wide-stack base, widestack limit, wide-frame pointer, and wide-stack pointer registers maintain data describing
the system stack. The segment base registers, logical address register and state page pointer registers contain
information used for memory address translation and virtual memory management. The processor status register
stores overflow and interrupt data describing the current processor state.
3.2.4 Address Translation Unit
The address translation unit (ATU) performs logical-to-physical address conversions, allowing the system to
access up to 32 Mbytes of physical memory. When an instruction address is in the program counter pipeline, the
ALU calculates its effective 31-bit logical address, stores it in the logical address register (LAR), and then passes
the address to the ATU. If the ATU is off, no address translation occurs and the ATU interprets the logical
address as a physical address. If the ATU is on, and in the physical mode, it translates the logical address into a
physical address. These same processes occur when an instruction in the instruction register pipeline requires
access to memory.
To efficiently perform this conversion process, the ATU maintains a cache. This cache consists of a physical
address RAM (PA RAM) and a logical-address content-addressable-memory (LA CAM) that together store 16
pagetable entries along with the page-referenced, page-modified, and protection bits. These pagetable entries are
the physical page addresses for the 16 most recently referenced logical pages.
When the CPU needs to access memory, the ALU calculates an effective 31-bit logical address. The ATU verifies
that the current process is allowed to make the memory access; it then passes a portion of the logical address to
the LA CAM to determine if the translation for this logical page address is in the PA RAM. If a translation is
there, the ATU reads the translation from the PA RAM and tests for read, write, and execute protection faults. If
a translation is not in the PA RAM, the CPU retrieves the necessary translation (pagetable entry) from the
memory and stores it in the PA RAM. If the PA RAM is already full, then the retrieved entry replaces one of the
entries in the PA RAM. A modified first-in first-out algorithm determines which entry is replaced.
The CPU retrieves translations from memory using single- and double-level pagetables. First, the CPU accesses
the segment base register specified by the local address. This register contains the physical address of the
beginning of a pagetable stored in memory. The logical address itself supplies an offset into the pagetable for a
specific pagetable entry. The CPU constructs the physical address of the pagetable entry and retrieves the entry
from memory. If the pagetable is first level, the retrieved entry is the desired translation. If the pagetable is
second level, the entry provides the physical address of the start of a first level pagetable and the CPU must repeat
the process to retrieve the desired translation.
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