ATU Status Bits
The ATU keeps two bits indicating its status. These bits are: ATUON and NPM.
The ATUON bit if set, indicates that all logical addresses should be translated to produce a physical address.
Also, all protection violations should be checked. The bit is set and reset by the microcode. When the ATU is
off, all addresses are passed through the ATU and protection checks are disabled.
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The NPM (Non-Physical Mode) bit if set, makes all memory accesses to generate non-physical space addresses
(no translation). Protection fault detection is inhibited. When NPN is set, ATUON bit is disregarded. The NPM
bit will normally be in the reset state.
These protection faults and all page faults are checked by the microcode which stores an appropriate error code
when a fault is detected.
3.2.5 Instruction Prefetcher
The instruction prefetcher prefetches instructions from main memory. It is the lowest priority requestor of the
S-bus. However, whenever the S-bus is not used by another requestor, a prefetch is initiated to achieve
maximum performance. The instruction prefetcher contains a multistage pipeline used to accelerate instruction
execution. The pipeline allows the SPU to overlap instruction fetches with instruction executions. This technique
accelerates program execution when instructions are sequential in memory. The CPU flushes the pipeline when
an instruction alters the program flow or modifies a location in the page from which the instruction came.
The instruction prefetcher consists of the instruction register (IR) pipeline, program counter (PC) pipeline, and
data latches. The PC pipeline tracks the memory locations of the instructions being fetched, being executed, and
those previously executed. The IR pipeline is a double first7jri-first-out queue consisting of five_167-bit_storage
elements containing prefetched instructions at various _stages of decode and execution
As the entry point to the pipeline, the instruction prefetcher retrieves the next assembly-language instruction and
passes it to the uSEQ decode logic. The logic decodes the instruction into a starting address of the appropriate
microroutine located in the SPU control store. As one instruction passes to the uSEQ for the beginning of the
execution phase, others are in different stages of decoding.
3.2.6 Control Unit
The control unit of the CPU coordinates the selection and execution of microcode used within the CPU. This unit
uses a two-level microcode technique for execution of instructions. The two levels are 32-bit wide vertical
microinstructions and 64-bit wide horizontal control words. The horizontal control words are stored in the
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CPU-resident horizontal programmable logic, array (HPLA). As a vertical microinstruction executes, the uSEQ
sends a 24-4bit
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vertidal Word to the horizontal sequencer in the CPU. The horizontal sequencer uses this vertical
word to initiate one or more horizontal control words. The vertical microinstruction, along with a sequence of
horizontal control words, drives the CPU logic to complete the execution of the originally fetched,
assembly-language instruction and keeps the pipeline operating.
3.2.7 CPU-FPU Synchronization
When the uSEQ decodes a floating-point instruction, the sequencing of both the CPU and FPU must be
synchronized. As the microroutine used to execute the assembly-language instruction begins, a vertical
microinstruction invokes both units simultaneously. The CPU then generates the memory address required for a
memory access and signals to the FPU when to take data on or off the system bus.
043-003621
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DGC CONFIDENTIAL - INTERNAL USE ONLY
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