The CPU instruction prefetcher enables instructions to be prefetched and partially decoded while another
instruction is being executed. This unit fetches double-word, assembly language instructions from system
memory. The uSEQ and CPU then load the assembly-language instructions from the S-bus into their respective
instruction register (IR) pipelines.
As the execution of each assembly-language instruction is completed, the uSEQ decodes the next instruction in its
IR pipeline. The information from the IR pipeline is sent to the uSEQ decode logic which responds by providing a
vertical microinstruction and a sequencing instruction. The vertical microinstruction is the first microinstruction of
the microroutine which the execution chips (CPU and FPU) use to execute the assembly-language instruction.
The sequencing instruction supplies the address of an entry in the control store that contains the next vertical
microinstruction in the microroutine and a further sequencing instruction.
The vertical microinstructions, whether from the uSEQ decode logic or the control store, form the first level of the
two-level ECLIPSE MV/7800 microcode scheme. These microinstructions supply horizontal addresses, each of
which specifies a location in the 256-word horizontal microcode space. The horizontal microcode space is the
second
s
level of the ECLIPSE MV/7800 microcode scheme, and is shared by the CPU and FPU chips. This
microcode space contains the horizontal control words that provide the control signals that direct the execution
chips to perform the data manipulations specified by the assembly-language instruction. After each
assembly-language instruction has been executed, the decode/execute cycle begins again. Figure 3-4 shows the
major functional elements of the SPU:
•
Central Processing Unit (CPU)
•
Microsequencer (uSEQ)
•
Control store
•
Floating-point unit (FPU)
043-003621
3-8
DGC
CONFIDENTIAL - INTERNAL USE ONLY
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