subsystem. The actual control operation sequences are not in the MCU gate array itself, but are stored in external
PROMs.
Physically, the MCU has been designed from a gate array which uses emitter-coupled logic (ECL) technology.
External hardware required for the MCU includes two 512 X 8 PROMs to store memory control sequences, four
registered transceivers to store data and addresses, and row and column address select (RAS and CAS) logic.
3.2.10.5 Data Unit - The major function of the data unit is performing ERCC functions. As each double-word
is placed on the bus for writing to memory, it is read into ERCC circuitry in the MCU and several check or C bits
are generated. These C bits are stored in memory along with the data word. When the double-word is
subsequently read from memory, it is read into the ERCC logic again along with the C bits. These original C bits
are compared with C bits newly generated from the data word. The results of this comparison are several
syndrome or S bits used to identify which bit, if any, is in error. The ERCC logic corrects any single-bit error and
detects, but does not correct all two bit errors and many other multiple-bit errors. When an error is detected
during a read operation, the requesting device is required to wait one cycle (320 nanoseconds) for the data to be
corrected and put back on the bus.
The MCU performs double-word reads as well as byte, word, and double-word writes. Byte and word writes are
complicated because error checking and correction is performed across a complete double-word at a time. When
a single word or byte is written to memory, the C bits are still generated on the basis of the entire 32-bit
double-word. The 32-bit word in memory is read into the ERCC logic, checked, and corrected if necessary. The
new data is then merged into double-word in the ERCC circuit and new C bits are generated. Both the data and
the C bits from the ERCC logic are placed back on the bus and written to memory. The writing of a single word or
byte (partial write) takes two cycles (640 nanoseconds).
3.2.10.6 Address Unit - The address unit logic includes a 32-bit output multiplexor, refresh address counter,
and syndrome save latch. The 32-bit output multiplexor selects one of three inputs to be placed on the M-bus.
The three inputs are outputs from either the ERCC logic in the data section, the refresh address counter, or the
syndrome save latch. The refresh address counter is a 23-bit ripple counter that is incremented for each refresh
operation.
Refresh and Sniffing
The dynamic RAMs that make up the memory array must be refreshed once every four milliseconds. To
accomplish this, one row out of 256 is refreshed every 15.4 microseconds. During refresh, one double-word
location from the row is read into the ERCC logic, checked, and corrected if necessary. This process is called
sniffing. Each time a particular row is refreshed, a different location is checked (sniffed). In this manner, each
location in memory is checked and corrected, if necessary, once every two minutes.
The MCU initiates memory refresh operations. When a refresh is due to occur, the MCU asserts a signal that
removes priority from all other devices using the system bus. When the current system bus operation is
completed, the MCU puts an address on the M-bus from its refresh address counter, and reads back the data at
the address into the ERCC logic for checking. IF an ERCC error is detected, the corrected data is written back
into the memory, and the error address and syndrome bits are saved in the error address register. The CPU can
read the contents of this register at any time by reading MCU local space.
The MCU can have its priority withheld for an extended length of time because the system bus can be locked by
the CPU, PIO/DCH controller, or BMC controller. This causes refresh operation to be postponed long enough to
violate the refresh specification for the memory RAMs. To prevent this situation, the MCU internally signals a
fault if it does not receive priority after 5 microseconds and performs the refresh even though it still has priority
withheld. If the CPU, PIO/DCH controller, or BMC controller tries to perform a memory operation by placing an
address on the bus during a refresh operation, the address is stored in the registered transceivers. Once the MCU
is off the bus, the operation is performed.
043-003621
3-18
DGC CONFIDENTIAL - INTERNAL USE ONLY
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