3.2.13.1 Operational Overview - The burst multiplexor channel is used to transfer bursts of data at high speed
between system memory and an I/O device controller once the device has been set up using PIO commands.
A BMC transaction begins with a device controller asserting one of eight dedicated BMC request lines. If more
than one request line is asserted, the BMC controller accepts the request from the device controller assigned to
the highest-numbered request line. As soon as its request is accepted, the selected device controller transfers a
21-bit address and a 12-bit channel control word to the BMC controller. The channel control word consists of an
eight-bit word count, specifying the number of words to be transferred, plus the control signals that specify the
nature of the transaction.
Following the transfer of the address and control word, the device controller transfers the specified data. One
16-bit word of data is transferred to the BMC controller with each BMC cycle until the number of words specified
has been transferred. The BMC controller governs the rate of data transfer. At the completion of the data
transfer, the BMC controller indicates that it is ready for another BMC request. Figure 3-10 shows the major
functional elements of the BMC controller.
Burst Multiplexor Channel Bus
The burst multiplexor channel bus is a data transfer bus that allows peripheral controllers to access memory
directly at a higher speed (up to 12 Mbytes) than
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the data channel. The bus consists of a 21-bit BMC address
bus, a 16-bit BMC data bus, an eight-bit word count bus, eight BMC request lines, and 11 separate control
signals, making a total of 64 signals. Data and word counts are multiplexed to prevent the transfer of an address
and a control word from occurring at the same time as the final data transfer of a previous transaction. Thus, an
address transfer cannot occur simultaneously with a data transfer.
BMC Control
Device controllers using the BMC channel operate synchronously based on a synchronization signal that the BMC
controller generates when data is available for input or output. A BMC state machine and its associated logic,
requests the S-bus when necessary, and determines the BMC operation based on the availability of the S-bus.
BMC Map
Before accessing memory, the BMC controller identifies the location in physical memory that receives or supplies
the data. One bit of the channel control word indicates how this physical memory addressing is accomplished. If
this mapping enable bit is not asserted, the 21-bit address supplied by the device controller is zero extended to 26
bits and used to access physical memory directly (unmapped address). If the mapping enable bit is asserted, the
most-significant address bit is ignored and the remaining 20 bits of the address are regarded as a logical address
(mapped address) that the BMC controller translates into a physical address before accessing memory. The BMC
controller performs this logical to physical address translation by accessing the BMC map. It uses the ten
most-significant bits of the 20-bit logical address as an index to specify one of the 1024 possible BMC map
entries.
BMC Map Pointer
In the ECLIPSE MV/7800 computer, the BMC map is located in a portion of system memory called the state
page. The entire BMC map requires two pages of system memory. For ease of implementation, the BMC map
begins on an even-page boundary, allowing its location in memory to be specified by a 16-bit physical page
address. The BMC controller keeps a copy of this physical page address in a 16-bit internal register called the
BMC map pointer. The physical memory address for any given map entry is generated by appending a zero to the
least-significant bit of the 10-bit index portion of the logical address, and combining it with the contents of the
BMC map pointer.
DGC CONFIDENTIAL - INTERNAL USE ONLY
3-27
043-003621
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