TO/FROM
BMC DEVICE
CONTROLLERS
BMC ADDRESS
BMC DATA
BMC CONTROL
DATA OUT LATCHES I
I ADDRESS INCREMENT
LOGIC
I
I WORD I
COUNT
I MAP CACHE j<
TAGS
\
7
MAP CACHE1
>
I DATA I N 1
:
A
T:
H
U
I
E
\
1
ENTRIES
LATCHES
.
MAP
POINTER
I
SYSTEM BUS
CONTROL
I
SYSTEM BUS INTERFACE
I
STATUS
REGISTER
\/ >
TO/FROM
SYSTEM
MEMORY
SYSTEM BUS (SBUS <0-32>)
FS- 12755
Figure 3-10. BMC Controller, Block Diagram
BMC Map Cache
A device controller that accesses system memory over the BMC bus typically transfers a block of data to or from
adjacent locations in memory. The BMC controller takes advantage of the sequential nature of these memory
accesses by saving the most recently used address translations in the BMC map cache. Each logical address
supplied by a device controller is compared to an entry in this cache, also associated with the particular device
controller, to determine if the required address translation is present within the cache. The BMC map in system
memory is accessed only when the cache does not have a copy of the required address translation.
043-003621
3-28
DGC CONFIDENTIAL - INTERNAL USE ONLY
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