The BMC map cache contains a total of four entries, each consisting of a tag field, identifying which map
entry is present, and a data field containing a copy of the map entry itself. The tag field of the map cache
entry contains a 10-bit logical page address and a validity bit.
The validity bit indicates whether the map cache entry contains a valid address translation. If a map cache
entry's validity bit is set, the tag fields's 10-bit logical page address is compared with the 10 most-significant
bits of any logical address supplied by that cache entry's assigned device controller. A Successful comparison
indicates that the desired map entry is contained in the data field of the map cache entry. The data field
contains a 16-bit physical page address. If the cache entry's validity bit is not set, or if the address
comparison is not successful, the BMC controller accesses the BMC map in system memory to retrieve the
map entry needed for the address translation. The BMC controller uses this map entry for address translation
and to update the BMC map cache entry.
BMC Map Access
A mechanism is provided that allows intelligent BMC devices to read or write BMC map slots directly. If the BMC
control bit, EXTEND, is asserted when an address and control word are sent to the BMC controller, the BMC
controller writes or reads the data to/from the map slots designated by the device address.
The address supplied by the BMC device specifies the initial map slot to read or write. Each map slot consists of
two 16-bit registers.
The word count supplied by the BMC device specifies both the number of 16-bit words to be transferred and the
number of registers to be loaded. Because two words are required to load or read each map slot, the starting
address and word count must be even to read or write a number of complete map slots.
BMC Input Data Buffering
The BMC controller's input buffering facility consists of four input data latches, parity and other associated logic
that collectively function in a first-in-first-out queue manner to move data from a BMC device to system memory.
This buffering logic, controlled by the BMC state machine, assembles single-word data into double-word data.
With this technique, BMC transfers to system memory are performed as 32-bit transfers even though the BMC
bus supplies data 16 bits at a time. Internal data buffering allows more efficient use of the S-bus so that full S-bus
bandwidth is utilized.
BMC Output Data Buffering
The BMC controller's output buffering facility consists of four output data latches, parity and other associated
logic that collectively function in a first-in-first-out queue manner to move data from system memory to the BMC
device. This buffering logic, controlled by the BMC state machine, accepts double-words of data from the S-bus
and supplies that data 16 bits at a time to the BMC bus.
BMC Controller Local Space
Transfers to or from the BMC controller from CPU microcode are performed by accessing BMC controller local
space. This nonphysical address space is specified by the assertion of bit 13 on the S-bus when a valid,
nonphysical address is indicated. This nonphysical address specifies a port address and individual local space
locations at the addressed port.
DGC CONFIDENTIAL - INTERNAL USE ONLY
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043-003621
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