DCH Map Pointer
The data channel map is located in a dedicated portion of system memory. The entire map of 512 entries requires
one page of system memory. For ease of implementation, the DCH map begins on a page boundary, allowing its
location in memory to be specified by a 16-bit physical page address. The DCH control logic keeps a copy of this
physical page address in a register called the DCH map pointer. The control logic generates the physical memory
address for a map entry by shifting the nine-bit index portion of the logical address left one bit and combining it
with the contents of the DCH map pointer.
DCH Map Cache
An I/O device controller uses the data channel to transfer multiple words of data to or from consecutive memory
location. The DCH control logic takes advantage of the sequential nature of data channel accesses by saving the
most recently used address translations in a DCH map cache.
The DCH map cache contains six fully associative entries. This size and configuration enables the cache to
operate effectively in an environment where several different I/O device controllers are in the process of
transferring blocks of data at any one time. Each DCH map cache entry consists of a tag field, identifying which
map entry is present; and a data field, containing a copy of the map entry itself.
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The tag field contains a nine-bit logical page address and a validity bit. The validity bit indicates whether the
particular cache entry contains a valid address translation. If the validity bit is set, the tag field's logical page
address is compared with the nine most-significant bits of the logical address supplied by the device controller. A
successful comparison indicates that the desired map entry is contained in the data field of the cache entry.
An unsuccessful comparison causes the DCH control logic to retrieve the required address translation from the
DCH map stored in system memory. When this occurs, a location in the DCH map cache is allocated to receive
the accessed map entry. Any unused cache locations are filled first, if all six cache locations contain valid DCH
map in memory.
The information contained in a DCH cache map entry is a copy of the information contained in the DCH map in
memory. The map load microcode assures that the contents of the cache remain accurate by invalidating a cache
entry when its corresponding map entry has been modified.
Use of the DCH map cache may be enabled or disabled by software that manipulates the appropriate bit in the
PIO/DCH control nester.
DCH Address and Input Data Buffering
The PIO/DCH chip provides input buffering that allows the DCH control logic to accept input data even when it is
temporarily unable to access the S-bus. This buffering allows the DCH control logic to accept a second input
operation's address and data while the PIO/DCH S-bus interface is requesting or actively using the S-bus for
either a DCH map access or the data transfer for the previous DCH input operation.
The DCH control logic can also accept the address for a third operation. If the third operation is an output
operation that does not require the S-bus to access memory, the operation may be completed and another address
accepted. However, if this third operation is an output operation requiring the S-bus, the DCH control logic must
wait until all memory accesses for the previous input operations are completed and then access memory as
needed. If the third operation is an input operation, data may not be accepted until the S-bus interface has
finished with the previous input operations.
DGC CONFIDENTIAL - INTERNAL USE ONLY
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043-003621
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