Asynchronous Line Controller
The asynchronous line controller provides the communication link between the CPU and the system console
terminal. It supports asynchronous communication at one of 16 available baud rates as specified by a four-bit
field in PIO/DCH control register.
The asynchronous line controller transfers data as eight-bit characters without hardware-enforced parity. The
receive and transmit sections of the controller are treated as two separate I/O devices allowing them to function
independently of one another. These two devices are referred 'to as the asynchronous line input (AL!), and the
asynchronous line output (ALO). The ALI receives eight-bit characters from the system console and places them
in a register that is read by a PIO instruction to device code 10. The ALO transmits eight-bit characters of data to
the system console. The data to be transmitted is specified by an I/O instruction to device code 11.
ECLIPSE Power Fail Monitor
The PIO/DCH controller monitors the power fail signal provided by the power supply and allows the CPU to
determine the state of this signal. The PIO/DCH controller will initiate a program interrupt from device code 0
whenever power fail is asserted. The device code 0 power fail interrupt has priority over any other interrupt in the
system and is not maskable. Device code 0 interrupts are inhibited when device code 45 power down mode is
enabled.
System Control
Program Error Log
Facility
The SCP error logging facility provides a uniform means for reporting hardware failures to the CPU for logging by
the operating system. It also allows system software to direct the operation of certain portions of the system
hardware, such as the memory subsystem's error checking and correction (ERCC) logic.
The SCP error log facility detects system power failures, memory ERCC errors, etc. This facility, together with the
microcode for the SCP and NMI handlers, reports these errors to the operating system by placing error
information in local memory and initiating a program interrupt. This facility responds to PIO commands to device
code 45.
3.2.11.11 DCH Control Logic - DCH control logic provides the data path and control for data
channel transfers
between the ECLIPSE I/O bus and the S-bus as a path to system memory. The CPU sets up multiple word
transfers to or from a DCH device by sending PIO commands to the PIO/DCH controller. Transfers are initiated
by an I/O device controller that supplies a 19-bit logical memory address to the data channel controller along with
control signals indicating the type of transfer. The DCH control logic translates the logical address into a physical
address using the data channel map, and performs the requested memory access.
DCH Map
The nine most-significant bits of the 19-bit logical address, supplied by the device controller, are used as an index
to specify one of 512 possible DCH map entries. DCH map entries are 32-bits wide. The 16 least-significant bits
of the map entry contain a 16-bit physical page address, which is combined with the 10 least-significant bits of the
19-bit logical address to form a 26-bit physical word address. This physical word address is used to perform the
required memory access for the data channel operation.
043-003621
3-24
DGC CONFIDENTIAL - INTERNAL USE ONLY
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