3.2.11.7 Non-maskable Interrupt (NMI) System - In the ECLIPSE MV/7800 system, a program executing in
the diagnostic remote processor performs console and diagnostic functions. This facility consists of special
microcode, referred to as the non-maskable interrupt (NMI) handler, the Intel 8031 microprocessor, and 8031
microcode.
The PIO/DCH chip assists in these console and diagnostic operations by implementing the I/O interface for device
45 and a system of hardware-specific interrupts referred to as non-maskable interrupts.
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The NMI handler and
8031 microcode, together with the hardware that the PIO/DCH chip implements to support them, are collectively
referred to as the system control program (SCP).
The PIO/DCH chip responds to events that should be brought to the attention of the CPU by signalling the uSEQ.
As a result, when the microsequencer tests for interrupts, control is transferred to the NMI handler microcode.
The portion of the NMI system utilized by the PIO/DCH controller can be enabled or disabled via the PIO/DCH
chip control register.
3.2.11.8 External NMIs - The PIO/DCH chip detects an NMI event through its internal logic or through
external hardware. Events that are detected internally include certain commands (such as Break) from the
asynchronous line controller or the power fail signal (if device 45 power fail is enabled). Memory ERCC errors
and other events (external NM's) are detected by hardware external to the PIO/DCH chip. Once an external
NMI is detected, the PIO/DCH chip determines its source. The NMI handler microcode then clears the request.
Information about NMIs is stored in the PIO/DCH controller's 16-bit system status register. The contents of this
register indicate the state of the power fail signal and whether the potential causes of the NMI is internal or
external to the PIO/DCH chip. The register contents are accessed by executing the appropriate I/O instruction.
3.2.11.9 PIO Priority - Since PIO and DCH operations share the ECLIPSE I/O bus, PIO operations are given
priority over DCH operations to prevent simultaneous bus operations. If either type of operation is currently in
--
progress it is allowed to finish. However, as long as an acknowledge to a DCH request has not been asserted, a
PIO operation request is given first priority.
3.2.11.10 Internal I/O Devices - The PIO/DCH controller contains several programmed I/O devices: the real
time clock (RTC), the programmable interval timer (PIT), the primary asynchronous line controller (ALC), and
the power fail monitor.
Real-Time Clock
The real-time clock generates interrupts at fixed intervals for use in performing time calculations. The frequency
of the interrupts is selectable to 10 Hz, 100 Hz, 1000 Hz, or the AC line frequency using an I/O instruction to
device code 14 (RTC). The PIO/DCH chip derives the required 10 Hz, 100 Hz, and 1000 Hz clocks from the
basic system clock.
Programmable Interval Timer
The programmable interval timer can be programmed to initiate program interrupts at fixed intervals and can be
examined by an I/0 instruction to device code 43 (PIT) at any point in its cycle to determine the time remaining
until the next interrupt. The PIT consists of a 16-bit initial count register and a 16-bit counter.
DGC
CONFIDENTIAL - INTERNAL USE ONLY
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