The data channel control logic within the PIO/DCH chip performs direct data transfers between the I/O bus and
system memory. A data channel map that contains the logical to physical address translations for these transfers
resides in physical memory. The PIO/DCH chip accelerates address translation by storing recently used address
translations from this map. It also enhances the performance of data channel output operations by prefetching
output data one double-word at a time from memory.
3.2.11.3 Configuration and Initialization - The PIO/DCH controller is initialized at power-up by asserting a
reset signal. Following initialization, the controller is configured for operation by setting a default bit in the
controller's 16-bit control register. This causes default values for the system operating frequency and other
parameters to be used in the controller's 32-bit configuration register and control register. Both registers are also
accessible as locations in PIO/DCH controller local space. Figure 3-9 shows the major functional elements of the
PIO/DCH controller:
•
S-bus interface
•
PIO control logic
•
Internal I/O devices
•
DCH control logic
3.2.11.4 System Bus (S-bus) Interface - The PIO/DCH controller resides on the S-bus as both bus requestor
and bus server. As server, it accepts PIO commands and output data in response to write operations from the
CPU, and supplies PIO input data in response to CPU-initiated read operations. Various internal control registers
may also be accessed with the PIO/DCH controller operating as bus server. As requestor, the PIO/DCH controller
performs data channel operations previously described. The PIO/DCH controller's activity as bus requestor is
limited to double-word read and single-word write operations.
When the PIO/DCH controller is the bus server, transfers to and from it are performed by addressing PIO/DCH
local space. This address space is specified by the assertion of bit 8 on the S-bus when a valid, nonphysical space
address is indicated. The nonphysical address specifies a port address and individual local space locations at that
address port.
3.2.11.5 PIO Control Logic - The PIO control logic decodes PIO commands and handles interrupts from the
PIO devices and the SCP error logging facility (device code 45). PIO operations executed by the PIO/DCH
controller are initiated by the transfer of a PIO command from the CPU to the PIO/DCH controller over the
systems bus. This transfer is accomplished by writing to the command register in the PIO control logic. If the PIO
command specifies an input operation, the CPU reads the PIO control logic input data register that contains the
desired input data. If the PIO command specifies an output operation, the CPU writes the output data to the PIO
control logic output data register. The PIO control logic then sends the data to the specified device over the
ECLIPSE I/O bus.
3.2.11.6 Programmed Interrupt Facility - The programmed interrupt receives PIO requests from PIO devices.
The inclusion of internal I/O devices in the PIO/DCH controller introduces slight irregularities in the operation of
the PIO system's interrupt priority mechanism. Each of the internal I/O devices in the PIO/DCH controller has a
higher interrupt priority than any of the external I/O devices. Therefore, the PIO/DCH controller inhibits external
I/O device interrupt acknowledgements whenever an internal I/O device is requesting a program interrupt.
The PIO/DCH controller implements an interrupt priority mechanism that does not require an interrupt priority
chain to pass from its internal devices to the external environment, but provides interrupt priority arbitration for
the internal PIO devices among themselves. The relative interrupt priority of the PIO/DCH internal I/O devices
from highest to lowest is: ECLIPSE power fail monitor, SCP error log facility, asynchronous line output,
asynchronous line input, real-time clock, and programmable interval timer. The intelligent power supply has the
next highest interrupt priority, followed by the external I/O devices. The external I/O device physically closest to
the PIO/DCH controller receives highest priority of the requesting external I/O devices.
DGC CONFIDENTIAL - INTERNAL USE ONLY
3-21
043-003621
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